Video | Oliver Jones on RISC-V: Spanning Datacenter to Edge
RISC-V is no longer a question of viability. It is becoming a mainstream architecture option across a growing range of SoC programs, from hyperscale AI and networking to edge AI, embedded processors, and microcontrollers entering volume production.
That was the central message from Aion Silicon CEO Oliver Jones in his talk, “RISC-V: Spanning Datacenter to Edge.” Jones discussed where RISC-V is gaining traction, why AI workloads are accelerating adoption, and what teams need to consider as they move from architecture decisions to production silicon.
Jones looks at how RISC-V is showing up in real SoC programs, and why the architecture conversation is becoming more practical.
What the talk covers:
- Where RISC-V is being used today, from datacenter AI accelerators to edge AI, networking, embedded systems, and MCUs
- Why many teams use RISC-V alongside Arm or x86 for control, orchestration, offload, and customization
- How AI workloads are changing the value of extensible compute architectures
- Why teams need to start with workload targets, modeling, memory behavior, and system constraints before deciding how much customization belongs in silicon
The key point: RISC-V is no longer just an ISA discussion. It is becoming a production architecture decision.
Across datacenter, AI, automotive, networking, edge, and embedded markets, Aion Silicon helps teams turn complex architecture decisions into production silicon, including through its Custom Silicon Architecture review.